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1 features replaces max660 and ltc?60 converts v+ to v- or v+ to 2v+ low output resistance, 4 ? typical high power efficiency selectable charge pump frequency - 10khz or 80khz - optimize capacitor size description the cat660 is a charge-pump voltage converter. it will invert a 1.5v to 5.5v input to a -1.5v to -5.5v output. only two external capacitors are needed. with a guaranteed 100ma output current capability, the cat660 can replace a switching regulator and its inductor. lower emi is achieved due to the absence of an inductor. in addition, the cat660 can double a voltage supplied from a battery or power supply. inputs from 2.5v to 5.5v will yield a doubled, 5v to 11v output voltage. a frequency control pin (boost/fc) is provided to select either a high (80khz) or low (10khz) internal oscillator frequency, thus allowing quiescent current vs. capacitor size trade-offs to be made. the 80khz frequency is selected when the fc pin is connected to cat660 100ma cmos charge pump inverter/doubler low quiescent current pin-compatible, high-current alternative to 7660/1044 industrial temperature range available in 8-pin soic, dip and 0.8mm thin 8- pad tdfn packages - lead-free, halogen-free package option ?2005 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 5000, rev. v applications negative voltage generator voltage doubler voltage splitter low emi power source gaas fet biasing lithium battery power supply instrumentation lcd contrast bias cellular phones, pagers typical application v+. the operating frequency can also be adjusted with an external capacitor at the osc pin or by driving osc with an external clock. both 8-pin dip and soic packages are available in the industrial temperature range. the tdfn package has a 4x4mm footprint and features a 0.8mm maximum height. compared to the 8-pin soic the tdfn package footprint is nearly 50% less. for die availability, contact catalyst semiconductor marketing. the cat660 replaces the max660 and the ltc ? 660. in addition, the cat660 is pin compatible with the 7660/ 1044, offering an easy upgrade for applications with 100ma loads. h a l o g e n f r e e tm l e a d f r e e 8 7 6 5 1 2 3 4 boost/fc cap+ gnd cap- v+ osc lv out cat660 +v in 1.5v to 5.5v inverted negative output voltage + voltage inverter 8 7 6 5 1 2 3 4 doubled positive output voltage + v in = 2.5v to 5.5v boost/fc cap+ gnd cap- v+ osc lv out positive voltage doubler c1 c1 cat660
cat660 2 doc. no. 5000, rev. v 8 7 6 5 1 2 3 4 boost/fc cap+ gnd cap- v+ osc lv out cat 660 8 7 6 5 1 2 3 4 boost/fc cap+ gnd cap- v+ osc lv out cat 660 pin descriptions circuit configuration pin number name inverter mode doubler mode boost/fc oscillator frequency open 10khz typical v+ 80khz typical, 40khz minimum 2 cap+ charge pump capacitor. positive terminal. same as inverter. 3 gnd power supply ground. power supply. positive voltage input. 4 cap- charge pump capacitor. negative terminal. same as inverter. 5 out output for negative voltage. power supply ground. 6 lv lv must be tied to out for all input voltages. 8 v+ power supply. positive voltage input. positive voltage output. frequency control for the internal oscilla- tor. with an external oscillator boost/fc has no effect. same as inverter. low-voltage selection pin. when the input voltage is less than 3v, connect lv to gnd. for input voltages above 3v, lv may be connected to gnd or left open. if osc is driven externally, connect lv to gnd. oscillator control input. an external capacitor can be connected to lower the oscillator frequency. an external oscillator can drive osc and set the chip operating frequency. the charge-pump frequency is one-half the frequency at osc. same as inverter. do not overdrive osc in doubling mode. standard logic levels will not be suitable. see the applications section for additional information. 7 osc oscillator frequency 10khz typical, 5khz minimum 80khz typical, 40khz minimum 1 boost/fc pin configuration 8 7 6 5 1 2 3 4 boost/fc cap+ gnd cap- v+ osc lv out cat 660 (top view) tdfn package: 4mm x 4mm 0.8mm maximum height soic package (s, x) tdfn package (rd8, zd8) dip package (p) ordering information part number package temperature range cat660epa 8 lead plastic dip -40 c to 85 c CAT660ESA 8-lead soic -40 c to 85 c CAT660ESA-te13 8-lead soic, tape & reel -40 c to 85 c cat660erd8 8-pad tdfn -40 c to 85 c cat660eva 8-lead soic (lead-free, halogen-free) -40 c to 85 c cat660eva-te13 8-lead soic (lead-free, halogen-free) -40 c to 85 c cat660ezd8 8-pad tdfn (lead-free, halogen-free) -40 c to 85 c (top view) (top view)
cat660 3 doc. no. 5000, rev. v absolute maximum ratings v+ to gnd ............................................................. 6v input voltage (pins 1, 6 and 7) .. -0.3v to (v+ + 0.3v) boost/fc and osc input voltage ........... the least negative of (out - 0.3v) or (v+ - 6v) to (v+ + 0.3v) output short-circuit duration to gnd .............. 1 sec. (out may be shorted to gnd for 1 sec without damage but shorting out to v+ should be avoided.) continuous power dissipation (t a = 70 c) plastic dip ................................................ 730mw soic ......................................................... 500mw tdfn ............................................................... 1w operating ambient temperature range cat660e .............. -40 c to 85 c storage temperature ......................... -65 c to 160 c lead soldering temperature (10 sec) ............. 300 c note: t a = ambient temperature these are stress ratings only and functional operation is not implied. exposure to absolute maximum ratings for prolongued time periods may affect device reliability. all voltages are with respect to ground. parameter symbol conditions min typ max units inverter: lv = open. r l = 1k ? 3.0 5.5 v supply voltage vs inverter: lv = gnd. r l = 1k ? 1.5 5.5 doubler: lv = out. r l = 1k ? 2.5 5.5 supply current is boost/fc = open, lv = open 0.09 0.5 ma boost/fc = v+ , lv = open 0.3 3 output current iout out is more negative than -4v 100 ma output resistance ro i l = 100ma, c1 = c2 = 150 f (note 2) 4 7 boost/fc = v+ (c1, c2 esr 0.5 ? ) ? i l = 100ma, c1 = c2 = 10 f12 oscillator frequency fosc boost/fc = open 5 10 khz (note 3) boost/fc = v+ 40 80 osc input current iosc boost/fc = open 1 a boost/fc = v+ 5 power efficiency pe r l = 1k ? connected between v+ and 96 98 % out, t a = 25 c (doubler) r l = 500 ? connected between gnd and 92 96 out, t a = 25 c (inverter) i l = 100ma to gnd, t a = 25 c (inverter) 88 voltage conversion veff no load, t a = 25 c 99 99.9 % efficiency note 1. in figure 1, test circuit capacitors c1 and c2 are 150 f and have 0.2 ? maximum esr. higher esr levels may reduce efficiency and output voltage. note 2. the output resistance is a combination of the internal switch resistance and the external capacitor esr. for maximum vo ltage and efficiency keep external capacitor esr under 0.2 ? . note 3. fosc is tested with c osc = 100pf to minimize test fixture loading. the test is correlated back to c osc =0pf to simulate the capacitance at osc when the device is inserted into a test socket without an external c osc . electrical characteristics v+ = 5v, c1 = c2 = 150 f, boost/fc = open, c osc = 0pf, inverter mode with test circuit as shown in figure 1 unless otherwise noted. temperature is over operating ambient temperature range unless otherwise noted.
cat660 4 doc. no. 5000, rev. v typical operating characteristics typical characteristic curves are generated using the test circuit in figure 1. inverter test conditions are: v+=5v, lv = gnd, boost/fc = open and t a = 25?c unless otherwise indicated. note that the charge-pump frequency is one- half the oscillator frequency. figure 1. test circuit 1 2 3 4 8 7 6 5 cat660 external oscillator c osc r l c2 150 f + v + 5v i s v + + c 1 150 f i l v out voltage inverter boost/fc cap+ gnd cap- v+ osc lv out output resistance vs. input voltage 0 2 4 6 8 10 123456 input voltage [v] output resistance [ ] . 100 load output resistance vs. temperature (50 ? load) 2 3 4 5 6 7 8 -50 -25 0 25 50 75 100 125 vin = 5v vin = 3v vin = 2v supply current vs. temperature (no load) 0 20 40 60 80 100 120 -50 -25 0 25 50 75 100 125 input current [ a] vin = 2v vin = 3v vin = 5v supply current vs. input voltage 0 30 60 90 120 150 123456 input voltage [v] input current [ a] . no load
cat660 5 doc. no. 5000, rev. v typical operating characteristics inverted output voltage vs. load, v+ = 5v 4.0 4.2 4.4 4.6 4.8 5.0 0 20406080100 load current [ma] inv. output voltage [v] . output voltage drop vs. load current 0.0 0.2 0.4 0.6 0.8 1.0 0 20406080100 load current [ma] output voltage [v] v+ = 5v v+ = 3v oscillator frequency vs. supply voltage 0 2 4 6 8 10 12 14 16 18 20 23456 supply voltage [v] frequency [khz] . lv = open lv = gnd boost = open oscillator frequency vs. supply voltage 0 50 100 150 200 23456 supply voltage [v] frequency [khz] bo o st = +v lv = open lv = gnd supply current vs. oscillator frequency 10 100 1000 10000 1 10 100 1000 oscillator frequency [khz] input current [ua] no load v+ = 5v
cat660 6 doc. no. 5000, rev. v the 1/fc1 term can be modeled as an equivalent impedance req. a simple equivalent circuit is shown in figure 3. this circuit does not include the switch resistance nor does it include output voltage ripple. it does allow one to understand the switch-capacitor topology and make prudent engineering tradeoffs. for example, power conversion efficiency is set by the output impedance, which consists of req and switch resistance. as switching frequency is decreased, req, the 1/fc1 term, will dominate the output impedance, causing higher voltage losses and decreased efficiency. as the frequency is increased quiescent current increases. at high frequency this current becomes significant and the power efficiency degrades. the oscillator is designed to operate where voltage losses are a minimum. with external 150 f capacitors, the internal switch resistances and the equivalent series resistance (esr) of the external capacitors determine the effective output impedance. a block diagram of the cat660 is shown in figure 4. the cat660 is a replacement for the max660 and the ltc660. figure 2. switched-capacitor building block figure 3. switched-capacitor equivalent circuit application information circuit description and operating theory the cat660 switches capacitors to invert or double an input voltage. figure 2 shows a simple switch capacitor circuit. in position 1 capacitor c1 is charged to voltage v1. the total charge on c1 is q1 = c1v1. when the switch moves to position 2, the input capacitor c1 is discharged to voltage v2. after discharge, the charge on c1 is q2 = c1v2. the charge transferred is: ? q = q1 - q2 = c1 (v1 - v2) if the switch is cycled "f" times per second, the current (charge transfer per unit time) is: i = f ? q = f c1 (v1 - v2) rearranging in terms of impedance: i= (v1-v2) v1-v2 (1/fc1) req = v1 c1 c2 r l v2 v1 c2 r l v2 req req = 1 fc1
cat660 7 doc. no. 5000, rev. v figure 4. cat660 block diagram + c2 v + (8) 2 osc boost/fc 8x (1) osc (7) lv (6) closed when v + > 3.0v gnd (3) cap - (4) c1 + cap + (2) sw2 sw1 vout (5) (n) = pin number oscillator frequency control the switching frequency can be raised, lowered or driven from an external source. figure 5 shows a functional diagram of the oscillator circuit. the cat660 oscillator has four control modes: boost/fc pin connection osc pin connection nominal oscillator frequency open open 10khz boost/fc= v+ open 80khz open or boost/fc= v+ external capacitor open external clock frequency of external clock if boost/fc and osc are left floating (open), the nominal oscillator frequency is 10khz. the pump frequency is one-half the oscillator frequency. by connecting the boost/fc pin to v+, the charge and discharge currents are increased, and the frequency is increased by approximately 8 times. increasing the frequency will decrease the output impedance and ripple currents. this can be an advantage at high load currents. increasing the frequency raises quiescent current but allows smaller capacitance values for c1 and c2. if pin 7, osc, is loaded with an external capacitor the frequency is lowered. by using the boost/fc pin and an external capacitor at osc, the operating frequency can be set. note that the frequency appearing at cap+ or cap- is one-half that of the oscillator. driving the cat660 from an external frequency source can be easily achieved by driving pin 7 and leaving the boost pin open, as shown in figure 6. the output current from pin 7 is small, typically 1 a to 8 a, so a cmos can drive the osc pin. for 5v applications, a ttl logic gate can be used if an external 100k ? pull-up resistor is used as shown in figure 6.
cat660 8 doc. no. 5000, rev. v vripple (mv) iout (ma) fosc (khz) c2 ( f) c2 esr ( ? ) 87 100 10 150 0.2 28 100 80 150 0.2 capacitor selection low esr capacitors are necessary to minimize voltage losses, especially at high load currents. the exact values of c1 and c2 are not critical but low esr capacitors are necessary. the esr of capacitor c1, the pump capacitor, can have a pronounced effect on the output. c1 currents are approximately twice the output current and losses occur on both the charge and discharge cycle. the esr effects are thus multiplied by four. a 0.5 ? esr for c1 will have the same effect as a 2 ? increase in cat660 output impedance. output voltage ripple is determined by the value of c2 and the load current. c2 is charged and discharged at a current roughly equal to the load current. the internal switching frequency is one-half the oscillator frequency. vripple = iout/(fosc x c2) + iout x esrc2 for example, with a 10khz oscillator frequency (5khz switching frequency), a 150 f c2 capacitor with an esr of 0.2 ? and a 100ma load peak-to-peak ripple voltage is 87mv. vripple vs. fosc figure 5. oscillator figure 6. external clocking boost/fc (1) lv (6) osc (7) ~18pf i 7.0 i 7.0 i i v + + -v + c2 1 2 3 4 8 7 6 5 required for ttl logic cat660 v + 100k osc input nc + c1 boost/fc cap+ gnd cap- v+ osc lv out
cat660 9 doc. no. 5000, rev. v capacitor suppliers the following manufacturers supply low-esr capacitors: manufacturer capacitor type phone web email comments avx/kyocera tps/tps3 843-448-9411 www.avxcorp.com avx@avxcorp.com tantalum vishay/sprague 595 402-563-6866 www.vishay.com aluminum sanyo mv-ax, ugx 619-661-6835 www.sanyo.com svcsales@sanyo.com aluminum nichicon f55 847-843-7500 www.nichicon-us.com tantalum hc/hd aluminum capacitor manufacturers continually introduce new series and offer different package styles. it is recommended that before a design is finalized capacitor manufacturers should be surveyed for their latest product offerings. the effective output impedance of a cat660 circuit is approximately: rcircuit rout 660 + (4 x esrc1) + esrc2 controlling loss in cat660 applications there are three primary sources of voltage loss: 1. output resistance vloss ? = iload x rout, where rout is the cat660 output resistance and iload is the load current. 2. charge pump (c1) capacitor esr: vlossc1 4 x esrc1 x iload, where esrc1 is the esr of capacitor c1. 3. output or reservoir (c2) capacitor esr: vlossc2 = esrc2 x iload, where esrc2 is the esr of capacitor c2. increasing the value of c2 and/or decreasing its esr will reduce noise and ripple.
cat660 10 doc. no. 5000, rev. v positive voltage doubler the voltage doubler circuit shown in figure 8 gives v out = 2 x v in for input voltages from 2.5v to 5.5v. figure 8: voltage doubler 1 2 3 4 8 7 6 5 cat660 + boost/fc cap+ gnd cap- v out = 2v in + v in 2.5v to 5.5v 1n5817* *schottky diode is for start-up only v+ osc lv out typical applications voltage inversion positive-to-negative the cat660 easily provides a negative supply voltage from a positive supply in the system. figure 7 shows a typical circuit. the lv pin may be left floating for positive input voltages at or above 3.3v. figure 7: voltage inverter + v out = -v in c2 1 2 3 4 8 7 6 5 cat660 nc + c1 v in 1.5v to 5.5v boost/fc cap+ gnd cap- v+ osc lv out
cat660 11 doc. no. 5000, rev. v precision voltage divider a precision voltage divider is shown in figure 9. with very light load currents under 100na, the voltage at pin 2 will be within 0.002% of v+/2 . output voltage accuracy decreases with increasing load. battery voltage splitter positive and negative voltages that track each other can be obtained from a battery. figure 10 shows how a 9v battery can provide symmetrical positive and negative voltages equal to one-half the battery voltage. figure 9: precision voltage divider (load 100na) 1 2 3 4 8 7 6 5 + v + 3v to 11v + boost/fc cap+ gnd cap- v+ osc lv out cat660 + 0.002% v + 2 i l < 100na figure 10: battery splitter + - (-4.5v) c2 150 f 1 2 3 4 8 7 6 5 cat660 + c1 150 f boost/fc cap+ gnd cap- v+ osc lv out + (4.5v) 3v < v bat < 11v v bat 9v battery v bat 2 v bat 2
cat660 12 doc. no. 5000, rev. v + c2 2 3 4 8 5 cat660 "1" + c1 + cat660 "n" 2 3 4 8 5 c1 +v in r out (of "n" cat660 s)= r out (of the cat660) n (number of devices) parallel operation paralleling cat660 devices will lower output resistance. as shown in figure 12, each device requires its own pump capacitor, c2, but the output reservoir capacitor is shared with all devices. the value of c2 should be increased by a factor of n, where n is the number of devices. the output impedance of the combined cat660's is: figure 12: paralleling devices reduce output resistance cascade operation for higher negative voltages the cat660 can be cascaded as shown in figure 11 to generate more negative voltage levels. the output resistance is approximately the sum of the individual cat660 output resistance. v out = -n x v in , where n represents the number of cascaded devices. figure 11: cascading to increase output voltage + c2 2 3 4 8 5 cat660 "1" + c1 + cat660 "n" 2 3 4 8 5 c1 +v in + c2 v out = -nv in
cat660 13 doc. no. 5000, rev. v notes: 1. complies with jedec publication 95 ms001 dimensions; however, some of the dimensions may be more stringent. 2. all linear dimensions are in inches and parenthetically in millimeters. package mechanical drawings 8-lead 150 wide soic (s, x) 8-lead 300 mil wide plastic dip (p) dimension d pkg min max 8l 0.1890(4.80) 0.1968(5.00) dimension d pkg min max 8l 0.355 (9.02) 0.400 (10.16) 0.149 (3.80) 0.1574 (4.00) 0.2284 (5.80) 0.2440 (6.20) 0.0532 (1.35) 0.0688 (1.75) 0.0040 (0.10) 0.0098 (0.25) 0.050 (1.27) bsc 0.013 (0.33) 0.020 (0.51) 0.0099 (0.25) 0.0196 (0.50) 0.0075 (0.19) 0.0098 (0.25) 0.016 (0.40) 0.050 (1.27) 0 ? -8 ? x 45 ? d 0.180 (4.57) max 0.015 (0.38) 0.100 (2.54) bsc 0.014 (0.36) 0.022 (0.56) d 0.245 (6.17) 0.295 (7.49) 0.045 (1.14) 0.060 (1.52) 0.110 (2.79) 0.150 (3.81) 0.120 (3.05) 0.150 (3.81) 0.300 (7.62) 0.325 (8.26) 0.310 (7.87) 0.380 (9.65)
cat660 14 doc. no. 5000, rev. v 8-pad tdfn (rd8, zd8) note: 1. all dimensions are in mm. angles in degrees. 2. coplanarity applies to the exposed pad as well as the terminals. coplanarity shall not exceed 0.08mm. 3. warpage shall not exceed 0.10mm. 4. package length/package width are considered as special characteristic. (s) 0.75+0.05 a b 5 8 4.00+0.10 (s) 1 pin 1 index area 4.00+0.10 (s) 4 0.0-0.05 0.20 ref. c 5 dap size 3.5 x 2.4 8 0.10 max typ. 0.15 0.15 0.20 0.10 2.20+0.10 0.10 0.80 typ. (6x) 2.40 ref. (2x) 0.30+0.05 (8x) 0.50+0.10 (8x) 0.20 pin 1 id
cat660 15 doc. no. 5000, rev. v revision history date rev. reason 10/6/2003 r updated typical operating characteristics data plots 10/7/2003 s updated electrical characteristics - output resistance and supply current updated typical operating characteristics data plots 10/15/2003 t updated description - eliminated commercial temp range updated ordering information - eliminated commercial temp range updated operating ambient temperature ranges 1/20/2005 u changed ordering information for cat660exa to cat660eva changed ordering information for cat660exa-te13 to cat660eva-te13 04/22/2005 v removed preliminary information from data sheet header
cat660 16 doc. no. 5000, rev. v catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com publication #: 5000 revison: v issue date: 04/22/2005 copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete.

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